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4 12-bit and 4 16-bit octal dac with on-chip reference in 14-lead tssop ad5678 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features low power octal dac with four 16-bit dacs four 12-bit dacs 14-lead/16-lead tssop on-chip 1.25 v/2.5 v, 5 ppm/c reference power down to 400 na @ 5 v, 200 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale 3 power-down functions hardware ldac and ldac override function clr function to programmable code rail-to-rail operation applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage current sources programmable attenuators functional block diagram interface logic input register din ldac gnd v out h v dd ldac 1 v refin / v refout sync sclk ad5678 clr 1 1 ru-16 package only 1.25v/2.5v ref v out a v out b v out c v out d v out e v out f v out g dac register string dac a buffer input register dac register string dac b buffer input register dac register string dac c buffer input register dac register string dac d buffer input register dac register string dac e buffer input register dac register string dac f buffer input register dac register string dac g buffer input register dac register string dac h buffer power-down logic power-on reset 05299-001 figure 1. general description the ad5678 is a low power, octal, buffered voltage-output dac with four 12-bit dacs and four 16-bit dacs in a single package. all devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5678 has an on-chip reference with an internal gain of 2. the ad5678-1 has a 1.25 v 5 ppm/c reference, giving a full- scale output of 2.5 v; the ad5678-2 has a 2.5 v 5 ppm/c reference, giving a full-scale output of 5 v. the on-board reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a software write. the part incorporates a power-on reset circuit that ensures that the dac output powers up to 0 v and remains powered up at this level until a valid write takes place. the part contains a power-down feature that reduces the current consumption of the device to 400 na at 5 v and provides software-selectable output loads while in power-do wn mode for any or all dac channels. the outputs of all dacs can be updated simultaneously using the ldac function, with the added functionality of user- selectable dac channels to si multaneously update. there is also an asynchronous clr that clears all dacs to a software- selectable code0 v, midscale, or full scale. the ad5678 utilizes a versatile 3- wire serial interface that operates at clock rates of up to 50 mhz and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. the on-chip precision output amplifier enables rail- to-rail output swing. product highlights 1. octal dac (four 12-bit dacs and four 16-bit dacs). 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 14-lead/16-lead tssop. 4. power-on reset to 0 v. 5. power-down capability. when powered down, the dac typically consumes 200 na at 3 v and 400 na at 5 v.
ad5678 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac characteristics........................................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings............................................................ 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 18 theory of operation ...................................................................... 20 d/a section................................................................................. 20 resistor string............................................................................. 20 internal reference ...................................................................... 20 output amplifier........................................................................ 21 serial interface ............................................................................ 21 input shift register .................................................................... 22 sync interrupt .......................................................................... 22 internal reference register....................................................... 23 power-on reset.......................................................................... 23 power-down modes .................................................................. 23 clear code register ................................................................... 23 ldac function .......................................................................... 25 power supply bypassing and grounding................................ 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 11/05rev. 0 to rev. a change to general description ...................................................... 1 change to specifications.................................................................. 3 replaced figure 48 ......................................................................... 22 change to the power-down modes section ............................... 23 10/05revision 0: initial version
ad5678 rev. a | page 3 of 28 specifications v dd = 4.5 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 1. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5678 (dac c, d, e, f) resolution 12 12 bits relative accuracy 0.5 2 0.5 1 lsb see figure 11 differential nonlinearity 0.25 0.25 lsb guaranteed monotonic by design (see figure 12 ) ad5678 (dac a, b, g, h) resolution 16 16 bits relative accuracy 8 32 8 16 lsb see figure 5 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 6 ) zero-code error 1 9 1 9 mv all 0s loaded to dac register (see figure 17 ) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 18 ) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 1 9 1 9 mv dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk (external reference) 10 10 v due to full-scale output change, r l = 2 k to gnd or v dd 5 5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk (internal reference) 25 25 v due to full-scale output change, r l = 2 k to gnd or v dd 10 10 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short-circuit current 30 30 ma v dd = 5 v power-up time 4 4 s coming out of power-down mode; v dd = 5 v reference inputs reference input voltage v dd v dd v 1% for specified performance reference current 35 45 35 45 a v ref = v dd = 5.5 v (per dac channel) reference input range 0 v dd 0 v dd v reference input impedance 14.6 14.6 k per dac channel reference output output voltage ad5678-2 2.495 2.505 2.495 2.505 v at ambient reference tc 3 5 10 5 10 ppm/c reference output impedance 7.5 7.5 k logic inputs 3 input current 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 5 v input high voltage, v inh 2 2 v v dd = 5 v pin capacitance 3 3 pf
ad5678 rev. a | page 4 of 28 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments power requirements v dd 4.5 5.5 4.5 5.5 v all digital inputs at 0 or v dd , dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1.3 1.8 1.3 1.8 ma internal reference off v dd = 4.5 v to 5.5 v 2 2.5 2 2.5 ma internal reference on i dd (all power-down modes) 5 v dd = 4.5 v to 5.5 v 0.4 1 0.4 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a reduced code range of ad5678 12-bit dacs (code 32 to code 4,064) and ad5678 16-bit dacs (code 512 to code 65,024). output unloaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down.
ad5678 rev. a | page 5 of 28 v dd = 2.7 v to 3.6 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 2. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5678 (dac c, d, e, f) resolution 12 12 bits relative accuracy 0.5 2 0.5 1 lsb see figure 11 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 12 ) ad5678 (dac a, b, g, h) resolution 16 16 bits relative accuracy 32 16 lsb see figure 5 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 6 ) zero-code error 1 9 1 9 mv all 0s loaded to dac register (see figure 17 ) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 18 ) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 1 9 1 9 mv offset temperature coefficient 1.7 1.7 v/c dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk (external reference) 10 10 v due to full-scale output change, r l = 2 k to gnd or v dd 4.5 4.5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk (internal reference) 25 25 v due to full-scale output change, r l = 2 k to gnd or v dd 4.5 4.5 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short-circuit current 30 30 ma v dd = 3 v power-up time 4 4 s coming out of power-down mode; v dd = 3 v reference inputs reference input voltage v dd v dd v 1% for specified performance reference current 20 20 20 20 a v ref = v dd = 3.6 v (per dac channel) reference input range 0 v dd 0 v dd v reference input impedance 14.6 14.6 k per dac channel reference output output voltage ad5678-1 1.247 1.253 1.247 1.253 v at ambient reference tc 3 5 15 5 15 ppm/c reference output impedance 7.5 7.5 k
ad5678 rev. a | page 6 of 28 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments logic inputs 3 input current 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 3 v input high voltage, v inh 2 2 v v dd = 3 v pin capacitance 3 3 pf power requirements v dd 2.7 3.6 2.7 3.6 v all digital inputs at 0 or v dd , dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1.2 1.5 1.2 1.5 ma internal reference off v dd = 2.7 v to 3.6 v 1.7 2.25 1.7 2.25 ma internal reference on i dd (all power-down modes) 5 v dd = 2.7 v to 3.6 v 0.2 1 0.2 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a reduced code range of ad5678 12-bit dacs (code 32 to code 4,064) and ad5678 16-bit dacs (code 512 to code 65,024). output unloaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down.
ad5678 rev. a | page 7 of 28 ac characteristics v dd = 2.7 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 min typ max unit conditions/comments 3 output voltage settling time 6 10 s ? to ? scale settling to 2 lsb slew rate 1.5 v/s digital-to-analog glitch impulse 4 nv-s 1 lsb change around major carry (see figure 34 ) digital feedthrough 0.1 nv-s reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency = 10 hz to 20 mhz digital crosstalk 0.5 nv-s analog crosstalk 2.5 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 340 khz v ref = 2 v 0.2 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = 0x8400, 1 khz 100 nv/hz dac code = 0x8400, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typi cal at 25c.
ad5678 rev. a | page 8 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. table 4. limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync to sclk falling edge set-up time t 5 4 ns min data set-up time t 6 4 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore t 11 10 ns min ldac pulse width low t 12 15 ns min sclk falling edge to ldac rising edge t 13 5 ns min clr pulse width low t 14 0 ns min sclk falling edge to ldac falling edge t 15 300 ns typ clr pulse activation time 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. guaranteed by design and characterization; not production tested. 05299-002 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db31 t 9 t 10 t 11 t 12 t 14 1 asynchronous ldac update mode. 2 synchronous ldac update mode. clr t 13 t 15 v out db0 ldac 1 ldac 2 figure 2. serial write operation
ad5678 rev. a | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max ) +150c tssop package power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w lead temperature, soldering snpb 240c pb free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5678 rev. a | page 10 of 28 pin configuration and fu nction descriptions 05299-003 1 2 3 4 5 6 7 ad5678 v dd v out a v out c v refin /v refout v out g v out e 14 13 12 11 10 9 8 din gnd v out b v out h v out f v out d sclk top view (not to scale) sync figure 3. 14-lead tssop (ru-14) 05299-004 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sync v dd v out a v out g v out e v out c ldac din gnd v out b v out h v refin /v refout clr v out f v out d sclk ad5678 top view (not to scale) figure 4. 16-lead tssop (ru-16) table 6. pin function descriptions pin no. 14-lead tssop 16-lead tssop mnemonic description C 1 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultan eously update. alternatively, this pin can be tied permanently low. 1 2 sync active low control input. this is the frame sy nchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falli ng edges of the next 32 clocks. if sync is taken high before the 32 nd falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 2 3 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in pa rallel with a 0.1 f capacitor to gnd. 3 4 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 11 13 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 4 5 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 10 12 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 7 8 v refin /v refout the ad5678 has a common pin for reference input and reference output. when using the internal reference, this is the reference output pi n. when using an external reference, this is the reference input pin. the default fo r this pin is as a reference input. C 9 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code registerzero, midscale, or full scale. default setting clears the output to 0 v. 5 6 v out e analog output voltage from dac e. the outp ut amplifier has rail-to-rail operation. 9 11 v out f analog output voltage from dac f. the o utput amplifier has rail-to-rail operation. 6 7 v out g analog output voltage from dac g. the outp ut amplifier has rail-to-rail operation. 8 10 v out h analog output voltage from dac h. the outp ut amplifier has rail-to-rail operation. 12 14 gnd ground reference point for all circuitry on the part. 13 15 din serial data input. this device has a 32-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 14 16 sclk serial clock input. data is clocke d into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz.
ad5678 rev. a | page 11 of 28 typical performance characteristics code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 05299-011 v dd = v ref = 5v t a = 25c figure 5. inl16-bit dac code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k 05299-012 v dd = v ref = 5v t a = 25c figure 6. dnl16-bit dac code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 05299-013 figure 7. inl16-bit dac, 2.5 v internal reference code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 05299-014 figure 8. dnl 16-bit dac, 2.5 v internal reference code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 05299-015 v dd = 3v v refout = 1.25v t a = 25 c figure 9. inl16-bit dac, 1.25 v internal reference
ad5678 rev. a | page 12 of 28 code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 05299-016 v dd = 3v v refout = 1.25v t a = 25 c figure 10. dnl16-bit dac, 1.25 v internal reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05299-045 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c figure 11. inl12-bit dac dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 05299-046 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c figure 12. dnl12-bit dac code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 05299-047 figure 13. inl12-bit dac, 2.5 v internal reference code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 05299-048 figure 14. dnl 12-bit dac, 2.5 v internal reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05299-049 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25 c figure 15. inl12-bit dac, 1.25 v internal reference
ad5678 rev. a | page 13 of 28 code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 05299-050 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25 c figure 16. dnl12-bit dac, 1.25 v internal reference temperature ( c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 05299-017 v dd = 5v gain error full-scale error figure 17. gain error and full-scale error vs. temperature temperature ( c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 60 100 05299-018 0 offset error zero-scale error figure 18. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 05299-019 gain error full-scale error figure 19. gain error and full-scale error vs. supply voltage v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 05299-020 zero-scale error offset error t a = 25 c figure 20. zero-scale error and offset error vs. supply voltage i dd (ma) frequency 20 0 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 05299-021 2 4 6 8 10 12 14 16 18 v dd = 3.6v v dd = 5.5v figure 21. i dd histogram with external reference
ad5678 rev. a | page 14 of 28 i dd (ma) frequency 14 0 2.02 05299-022 2 4 6 8 10 12 v dd = 3.6v v dd = 5.5v 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 v refout = 1.25v v refout = 2.5v figure 22. i dd histogram with internal reference current (ma) error vol t age (v) 0.50 0.40 ?0.50 ?0.40 ?0.30 ?0.20 ?0.10 0 0.10 0.20 0.30 ?10 ?8 ?6 ?4 ?2 0 2 4 8 61 05299-023 0 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current figure 23. headroom at rails vs. source and sink current (ma) v out (v) 6.00 5.00 4.00 3.00 2.00 1.00 ?1.00 0 ?30 ?20 ?10 0 10 20 30 05299-024 v dd = 5v v refout = 2.5v t a = 25 c zero scale full scale midscale 1/4 scale 3/4 scale figure 24. ad5678-2 sour ce and sink capability current (ma) v out (v) 4.00 ?1.00 0 1.00 2.00 3.00 ?30 ?20 ?10 0 10 20 30 05299-025 v dd = 3v v refout = 1.25v t a = 25 c zero scale full scale midscale 1/4 scale 3/4 scale figure 25. ad5678-1 sour ce and sink capability code i dd (ma) 2.0 0 05299-026 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 512 10512 20512 30512 40512 50512 60512 t a = 25c v dd = v ref = 3v v dd = v ref = 5v figure 26. supply current vs. code temperature (c) i dd (ma) 1.6 0 0.2 1.0 1.2 1.4 0.4 0.6 0.8 ?40 ?20 0 20 40 60 80 100 05299-027 v dd = v refin = 3.6v v dd = v refin = 5.5v figure 27. supply current vs. temperature
ad5678 rev. a | page 15 of 28 v dd (v) i dd ( m a) 1.6 0 0.2 1.0 1.2 1.4 0.4 0.6 0.8 2.7 05299-028 3.2 4.2 3.7 5.2 4.7 t a =25c figure 28. supply current vs. supply voltage v logic (v) i dd (ma) 8 0 1 5 6 7 2 3 4 012345 05299-029 6 v dd = 5v v dd = 3v t a = 25c figure 29. supply current vs. logic input voltage 05299-030 time base = 4 s/div v dd = v ref = 5v t a = 25 c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 figure 30. full-scale settling time, 5 v 05299-031 ch1 2.0v ch2 500mv m100 s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25 c v out v dd 1 2 max(c2)* 420.0mv figure 31. power-on reset to 0 v 05299-032 ch1 2.0v ch2 1.0v m100 s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25 c v out v dd 1 2 figure 32. power-on reset to midscale 05299-033 v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 figure 33. exiting po wer-down to midscale
ad5678 rev. a | page 16 of 28 sample v out (v) 2.505 2.485 0 512 05299-034 64 128 192 256 320 384 448 v dd = 5v v refout = 2.5v t a = 25c 4ns/sample number glitch impulse = 3.55nv-s 1 lsb change around midscale (0x8000 to 0x7fff) 2.486 2.487 2.488 2.489 2.490 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 figure 34. digital-to-analog glitch impulse (negative) sample v out (v) 2.5000 2.4950 0 512 05299-035 2.4955 2.4960 2.4965 2.4970 2.4975 2.4980 2.4985 2.4990 2.4995 64 128 192 256 320 384 448 v dd = 5v v refout = 2.5v t a = 25c 4ns/sample number figure 35. analog crosstalk sample v out (v) 2.4900 2.4855 0 512 05299-036 64 128 192 256 320 384 448 2.4860 2.4865 2.4870 2.4875 2.4880 2.4885 2.4890 2.4895 v dd = 5v v refout = 2.5v t a = 25c 4ns/sample number figure 36. dac-to -dac crosstalk 05299-037 1 y axis = 2 v/div x axis = 4s/div v dd = v ref = 5v t a = 25 c dac loaded with midscale figure 37. 0.1 hz to 10 hz output noise plot, external reference 5s/div 10 v/div 1 05299-038 v dd = 5v v refout = 2.5v t a = 25 c dac loaded with midscale figure 38. 0.1 hz to 10 hz outp ut noise plot, internal reference 4s/div 5 v/div 1 05299-039 v dd = 3v v refout = 1.25v t a = 25 c dac loaded with midscale figure 39. 0.1 hz to 10 hz output noise plot, internal reference
ad5678 rev. a | page 17 of 28 frequency (hz) output noise (nv/ hz) 800 0 100 200 300 400 500 600 700 100 10000 1000 100000 1000000 05299-040 v dd =3v v refout =1.25v v dd =5v v refout =2.5v t a =25c midscale loaded figure 40. noise spectral density, internal reference frequency (hz) (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k 05299-041 v dd =5v t a =25c dac loaded with full scale v ref =2v0.3vp-p figure 41. total harmonic distortion capacitance (nf) time ( s) 16 14 12 10 8 6 4 01234567 9 81 05299-042 0 v ref = v dd t a = 25 c v dd = 5v v dd = 3v figure 42. settling time vs. capacitive load 05299-043 v out f v out b 3 ch3 5.0v ch4 1.0v ch2 1.0v m200ns a ch3 1.10v 2 4 4 clr figure 43. hardware clr frequency (hz) (db) 5 ?40 10k 100k 1m 10m 05299-044 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c figure 44. multiplying bandwidth
ad5678 rev. a | page 18 of 28 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. figure 5 , figure 7 , and figure 9 show plots of typical inl vs. code. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. figure 6 , figure 8 , and figure 10 show plots of typical dnl vs. code. offset error offset error is a measure of the difference between the actual v out and the ideal v out , expressed in millivolts in the linear region of the transfer function. offset error is measured on the ad5678 with code 512 loaded into the dac register. it can be negative or positive and is expressed in millivolts. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded into the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5678, because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in millivolts. figure 18 shows a plot of typical zero-code error vs. temperature. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded into the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed as a percentage of the full-scale range. figure 17 shows a plot of typical full-scale error vs. temperature. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 34 . dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v, and v dd is varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac. it is expressed in microvolts. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts per milliamp. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. channel-to-channel isolation channel-to-channel isolation is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in decibels. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but is measured when the dac is not being written to ( sync held high). it is specified in nv-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa.
ad5678 rev. a | page 19 of 28 digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5678 rev. a | page 20 of 28 theory of operation d/a section the ad5678 dac is fabricated on a cmos process. the archi- tecture consists of a string of dacs followed by an output buffer amplifier. the parts include an internal 1.25 v/2.5 v, 5 ppm/c reference with an internal gain of 2. figure 45 shows a block diagram of the dac architecture. 05299-005 dac register ref (+) v dd v out gnd ref (?) resistor string output amplifier (gain = +2) figure 45. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using an internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d = decimal equivalent of the binary code that is loaded to the dac register. 0 to 4,095 for ad5678 dac c, d, e, f (12 bits). 0 to 65,535 for ad5678 dac a, b, g, h (16 bits). n = the dac resolution. resistor string the resistor string section is shown in figure 46 . it is simply a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. 05299-006 to output amplifier r r r r r figure 46. resistor string internal reference the ad5678 has an on-chip reference with an internal gain of 2. the ad5678-1 has a 1.25 v 5 ppm/c reference, giving a full- scale output of 2.5 v. the ad5678-2 has a 2.5 v 5 ppm/c reference, giving a full-scale output of 5 v. the on-board reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a write to a control register. see table 7 . the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor be placed between the reference output and gnd for reference stability. individual channel power-down is not supported while using the internal reference.
ad5678 rev. a | page 21 of 28 output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . the amplifier is capable of driving a load of 2 k in parallel with 1,000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 24 and figure 25 . the slew rate is 1.5 v/s with a ? to ? scale settling time of 10 s. serial interface the ad5678 has a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 32-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5678 compatible with high speed dsps. on the 32 nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part. as is mentioned previously, however, sync must be brought high again just before the next write sequence. table 7. command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 update dac register n 0 0 1 0 write to input register n, update all (software ldac ) 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 load clear code register 0 1 1 0 load ldac register 0 1 1 1 reset (power-on reset) 1 0 0 0 set up internal ref register 1 0 0 1 reserved C C C C reserved 1 1 1 1 reserved table 8. address commands address (n) a3 a2 a1 a0 selected dac channel 0 0 0 0 dac a (16 bits) 0 0 0 1 dac b (16 bits) 0 0 1 0 dac c (12 bits) 0 0 1 1 dac d (12 bits) 0 1 0 0 dac e (12 bits) 0 1 0 1 dac f (12 bits) 0 1 1 0 dac g (16 bits) 0 1 1 1 dac h (16 bits) 1 1 1 1 all dacs
ad5678 rev. a | page 22 of 28 input shift register the input shift register is 32 bits wide. the first four bits are dont cares. the next four bits are the command bits, c3 to c0 (see table 7 ), followed by the 4-bit dac address bits, a3 to a0 (see table 8 ), and finally the 16-/12-bit data-word. the data- word comprises the 16-/12-bit input code followed by four or eight dont care bits for the ad5678 dac a, b, g, h and ad5678 dac c, d, e, f, respectively (see figure 47 and figure 48 ). these data bits are transferred to the dac register on the 32 nd falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for 32 falling edges of sclk, and the dac is updated on the 32 nd falling edge and rising edge of sync . however, if sync is brought high before the 32 nd falling edge, this acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurssee figure 49 . 05299-007 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x xxx db31 (msb) db0 (lsb) data bits figure 47. ad5678 input register content for dac a, b, g , h 05299-008 address bits command bits c3c2c1c0a3a2a1a0d11d10d9d8d7d6d5d4d3d2d1d0xxxxxxxx x xxx db31 (msb) db0 (lsb) data bits figure 48. ad5678 input register content for dac c, d, e, f 05299-009 sclk din db31 db0 invalid write sequence: sync high before 32nd falling edge valid write sequence, output updates on the 32nd falling edge db31 db0 sync figure 49. sync interrupt facility
ad5678 rev. a | page 23 of 28 internal reference register the on-board reference is off at power-up by default. this allows the use of an external reference if the application requires it. the on-board reference can be turned on/off by a user- programmable internal ref register by setting bit db0 high or low (see table 9 ). command 1000 is reserved for this internal ref set-up command (see table 7 ). table 11 shows the state of the bits in the input shift register corresponds to the mode of operation of the device. power-on reset the ad5678 contains a power-on reset circuit that controls the output voltage during power-up. the ad5678 output powers up to 0 v, and the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power-on reset code. command 0111 is reserved for this reset functionsee table 7 . any events on ldac or clr during power-on reset are ignored. power-down modes the ad5678 contains four separate modes of operation. command 0100 is reserved for the power-down function. see table 7 . these modes are software-programmable by setting two bits, bit db9 and bit db8, in the control register. table 11 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac h to dac a) can be powered down to the selected mode by setting the corresponding eight bits (db7 to db0) to 1. see table 12 for the contents of the input shift register during power-down/power- up operation. when using the internal reference, only all channel power-down to the selected modes is supported. when both bits are set to 0, the part works normally with its normal power consumption of 1.3 ma at 5 v. however, for the three power-down modes, the supply current falls to 400 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). the output stage is illustrated in figure 50 . the bias generator of the selected dac(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power- down. the time to exit power-down is typically 5 s for v dd = 5 v and for v dd = 3 v, see figure 33 . any combination of dacs can be powered up by setting pd1 and pd0 to 0 (normal operation). the output powers up to the value in the input register ( ldac low) or to the value in the dac register before powering down ( ldac high). clear code register the ad5678 has a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive . bringing the clr line low clears the contents of the input register and the dac registers to the data contained in the user-configurable clr register and sets the analog outputs accordingly. this function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. these clear code values are user-programmable by setting two bits, bit db1 and bit db0, in the clr control register. see table 13 . the default setting clears the outputs to 0 v. command 0101 is reserved for loading the clear code register, see tabl e 7 . the part exits clear code mode on the 32 nd falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. the clr pulse activation timethe falling edge of clr to when the output starts to changeis typically 280 ns. however, if the value is outside the linear region, it typically takes 520 ns after executing clr for the output to start changing. see figure 43 . see table 14 for contents of the input shift register during the loading clear code register operation.
ad5678 rev. a | page 24 of 28 table 9. internal reference register internal ref register (db0) action 0 reference off (default) 1 reference on table 10. 32-bit input shift register contents for reference set-up function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db1 db0 x 1 0 0 0 x x x x x 1/0 dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares internal ref register table 11. power-down modes of operation db9 db8 operating mode 0 0 normal operation power-down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state table 12. 32-bit input shift register contents for power-down/power-up function msb lsb db31 to db28 db27 db26 db25 db 24 db23 db22 db21 db20 db19 to db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x 0 1 0 0 x x x x x pd1 pd0 dac h dac g dac f dac e dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares power- down mode power-down/power-up channel selectionset bit to 1 to select resistor network v out v fb resistor string dac 05299-010 power-down circuitry amplifier figure 50. output stage during power-down table 13. clear code register clear code register db1 db0 cr1 cr0 clears to code 0 0 0x0000 0 1 0x8000 1 0 0xffff 1 1 no operation table 14. 32-bit input shift register contents for clear code function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db2 db1 db0 x 0 1 0 1 x x x x x cr1 cr0 dont cares command bits (c3 to c0) address bits (a3 to a0)dont cares dont cares clear code register
ad5678 rev. a | page 25 of 28 ldac function the outputs of all dacs can be updated simultaneously using the hardware ldac pin. synchronous ldac : after new data is read, the dac registers are updated on the falling edge of the 32 nd sclk pulse. ldac can be permanently low or pulsed as in figure 2 . asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. alternatively, the outputs of all dacs can be updated simulta- neously using the software ldac function by writing to input register n and updating all dac registers. command 0011 is reserved for this software ldac function. an ldac register gives the user extra flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that this channels update is controlled by the ldac pin. if this bit is set to 1, this channel updates synchronously; that is, the dac register is updated after new data is read, regardless of the state of the ldac pin. it effectively sees the ldac pin as being tied low. (see table 15 for the ldac register mode of operation.) this flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 0110 loads the 8-bit ldac register (db7 to db0). the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 means the dac channel is updated regardless of the state of the ldac pin. see tabl e 16 for the contents of the input shift register during the load ldac register mode of operation. power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5678 should have separate analog and digital sections. if the ad5678 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5678. the power supply to the ad5678 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should physically be as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board. table 15. ldac register load dac register ldac bits (db7 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin 1 xdont care dac channels update, overriding the ldac pin. dac channels see ldac as 0. table 16. 32-bit input shift register contents for ldac overwrite function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db8 db7 db6 db5 db4 db3 db2 db1 db0 x 0 1 1 0 x x x x x dac h dac g dac f dac e dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares setting ldac bit to 1 overrides ldac pin
ad5678 rev. a | page 26 of 28 outline dimensions 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 51. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 52. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range package description package option power-on reset to code accuracy internal reference ad5678bruz-1 1 ?40c to +105c 14-lead tssop ru-14 zero 16 lsb inl 1.25 v ad5678bruz-1reel7 1 ?40c to +105c 14-lead tssop ru-14 zero 16 lsb inl 1.25 v ad5678bruz-2 1 ?40c to +105c 16-lead tssop ru-16 zero 16 lsb inl 2.5 v ad5678bruz-2reel7 1 ?40c to +105c 16-lead tssop ru-16 zero 16 lsb inl 2.5 v ad5678aruz-2 1 ?40c to +105c 16-lead tssop ru-16 zero 32 lsb inl 2.5 v AD5678ARUZ-2REEL7 1 ?40c to +105c 16-lead tssop ru-16 zero 32 lsb inl 2.5 v 1 z = pb-free part.
ad5678 rev. a | page 27 of 28 notes
ad5678 rev. a | page 28 of 28 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05299C0C11/05(a)

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